SBIR Phase I: Wireless Sidestep Network: Harnessing Sub-terahertz to Enable New Degrees of Freedom in AI Data Center Architectures

The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is to address a critical infrastructure bottleneck constraining the growth of artificial intelligence. Modern artificial intelligence training facilities house hundreds of thousands of accelerator processors interconnected by millions of cables, which weigh hundreds of thousands of pounds, obstruct airflow, raise cooling costs, and require weeks to reconfigure. This project develops a high-speed wireless interconnect that operates as a transparent Ethernet link, eliminating thousands of management cables in each facility while providing a foundation for broader wireless adoption as the technology matures. The initial market is the management and control network, a segment representing several billion dollars in annual infrastructure spending, where operational pain is acute and performance requirements fall well within the capabilities of the proposed system. Beyond data centers, the underlying technology applies to smart factories requiring real-time robotic coordination, telecommunications backhaul, and enterprise networking. Success establishes domestic leadership in a foundational technology for next-generation wireless, reduces dependence on foreign suppliers for critical artificial intelligence infrastructure, and catalyzes a domestic semiconductor ecosystem, creating high-wage engineering positions and accelerating the deployment of artificial intelligence capabilities across the national economy. This Small Business Innovation Research (SBIR) Phase I project develops a real-time, 100 gigabit-per-second wireless transceiver operating in the 110 to 170 gigahertz band, packaged as a portable prototype that interfaces transparently with standard Ethernet infrastructure. The research objectives are threefold: achieve 100 gigabit-per-second throughput from a 33 gigabit-per-second baseline, integrate a transparent Ethernet bridge compatible with unmodified higher-layer protocols, and characterize the power and thermal budget to validate a path toward small-form-factor pluggable modules. The throughput target is achieved by combining three concurrent advances: migration to a next-generation radio-frequency system-on-chip that expands per-channel bandwidth, increasing the fast-Fourier-transform size, and increasing the modulation order. A lightweight medium access control layer and field-programmable bridge present a standard Ethernet interface to the host, while a purpose-built air-interface protocol manages adaptive equalization, rate adaptation, and burst-error recovery. Anticipated results include sustained operation below a bit-error rate of 10⁻⁶ over a multi-meter link, end-to-end latency under 100 microseconds, and verified interoperability with commercial management traffic. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.