High-Density Electrical Interconnect Technology for NuclearPhysics

The DOE Office of Nuclear Physics (NP) seeks new developments in detector instrumentation electronics with significantly improved energy, position, timing resolution, sensitivity, rate capability, stability, dynamic range, durability, background suppression, programmability and functionality. Next-generation detectors will be needed for the 12 GeV Continuous Electron Beam Accelerator Facility (CEBAF) Upgrade at the Thomas Jefferson National Accelerator Facility (TJNAF), at the future Facility for Rare Isotope Beams (FRIB) under construction at Michigan State University, at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Lab, and at a proposed future Electron-Ion Collider (EIC). The large amounts of data required from detectors in these experiments require large parallel interconnects. The demands on next-generation nuclear physics tracking detectors in terms of pixel size, mass budget, data rate, and front-end processing are increasing. New technologies are needed for reducing cost while increasing the density of interconnection of pixelated sensors to readout electronics by enhancing or replacing solder bump-based technologies. Many next-generation detectors will have highly segmented electrode geometries with 5-5000 channels per square centimeter, covering areas up to several square meters. Conventional packaging and assembly technology cannot be used at these high densities. Technologies are sought that can enable efficient cooling and/or enable wafer-to-wafer interconnection, by utilizing 3D integration with through-silicon vias or other methods. In this SBIR, Vega Wave Systems, Inc. will adapt its proprietary 3D silicon interconnect technology for the requirements of Nuclear Physics. In addition to the needs of the Nuclear Physics community, there are several main-stream commercial applications for high-density interconnects based upon silicon 3DIC technology. Vega Wave Systems, Inc. proposes to further develop the high-density electrical interconnect technology it invented in a previous DOE SBIR. The proprietary interconnect technology complements bump bonding used in 3DIC manufacturing. This new process is low cost, rapidly manufacturable, high strength interconnect process that can be performed at both the wafer level and for individual die. A wide range of aspect ratios will allow the manufacturing of complex 3D multi-chip modules (3D MCMs). This technology has both commercial and high-energy physics applications. The technology developed here will advance the state of electronics and optoelectronic packaging by connecting two dimensional chips by the third dimension. This is applicable in high density memory, high density processing, high speed optical interconnects and direct integration of components current connected via printed circuit boards.