SBIR Phase I: Manufacturable Growth And Purification Of Aligned, Semiconducting Carbon Nanotubes

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to enable the development of monolithic 3D integration of carbon nanotube (CNT) computing in conjunction with silicon nanoelectronics. The value of nanoelectronics utilizing silicon integrated with CNT has been shown to have immense potential through various academic studies. However, the transition of this technology from academia to industry has been stymied by lack of CNT material that meets the manufacturing requirements particularly in terms of alignment, purity, and compatibility to be properly explored. Monolithic 3D integration will enable game-changing levels of improvement to computing speed and power efficiency, creating better computing for all. Providing a material which accelerates research and development for improved computing will create a game changing impact on the $500B integrated circuit market and potentially create billions of dollars in revenue. This project is focused on the needs of the nanoelectronics industry because of the impact possible in that market, but other markets such as biosensing or flexible electronics would benefit from the same materials and often at relaxed specifications. This Small Business Innovation Research Phase I project will greatly expand the utilization of carbon nanotubes (CNTs) in nanoelectronics by making industrially relevant material available. This will allow application oriented nanoelectronics teams to move forward with R&D projects. Further, the project's work on the fundamentals of aligned CNT growth and purification will benefit the CNT materials community by the extension of the material into commercial manufacturing. The research objectives are on two fronts: 1) growth of CMOS compatible aligned CNTs and 2) purification of aligned CNTs. Growth of highly aligned CNT populations has typically utilized catalysts which are not compatible with front end of line CMOS fabrication, hindering the use of material in conjunction with Si integrated circuits. Current methods of CNT purification to remove metallic CNTs suffer from either destroying the critical CNT alignment, utilization of non-CMOS compatible materials, or the need of extensive post-processing. This project will develop a growth process and a purification process that preserves alignment while maintaining CMOS compatibility and utilizes wafer scale batch processes that allow high throughput manufacturing. The purification scheme is a proprietary method which must be characterized and refined to meet the exacting purification standards of 99.99% semiconducting CNTs or better. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.