STTR Phase I: Enhancing IoT's Connected Device Capabilities using High-Performance Low-Power RRAM-based FPGAs

The broader impact/commercial potential of this Small Technology Transfer Research (STTR) Phase I project lays in its ability to enable reconfigurable hardware acceleration in the Internet-of-Things (IoT). Users under constrained power at the edge will be able to choose a new solution that can bring acceleration, and enable datacenter like capabilities, and benefit from the IoT's long-sought promise. Using Resistive Random-Access Memory (RRAM) to develop a next-generation Field Programmable Gate Array (FPGA), increasing performance while reducing energy consumption at the sensor node level, is possible. As already experienced in our data driven world, it is critical that we improve our computing capabilities at the edge in order to gain in responsiveness and increase our energy efficiency. With evermore data and performance requirements to deliver on the consumer demands, innovative uses of emerging memories are showing great promise and providing capabilities that will help fulfill the IoT's potential. If fulfilled, this technology has the potential to enable a whole set of data driven applications at the edge, such as low-energy image recognition and learning in drones to operate longer and more effectively or long-lasting medical implants with leading data aggregation and reactiveness. This Small Technology Transfer Research (STTR) Phase I project will aim to commercialize a patented technology to realize a ultra-low-power Field Programmable Gate Array (FPGA) based on Resistive Random-Access Memory (RRAM). To handle the data explosion in Internet of Things (IoT) network, the industry is moving towards increasing intelligent analysis capability for single IoT devices. Tight power budget has become a critical road block: high-end solutions, such as multicore CPUs, GPUs, can provide enough computing capability but fail to meet the power budget, while low-power commercial products, such as micro-controllers and low-power FPGAs, can satisfy power constraints but hardly follow the increasing complexity in data analysis algorithms. This project aims to develop a ultra-low-power FPGA that can offer high-performance data analysis capability under IoT-level power limits. This project will prototype a FPGA chip built around an innovative RRAM-based routing multiplexer design. We will also release an associated software tool suite to support the implementation of customer's applications on the technology. Compared to existing commercial solutions, the proposed FPGA product is expected to demonstrate similar computing capability as high-end FPGA solutions while satisfying an IoT power budget (<1W). This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.