Neuromorphic Processors for Next Generation Systems

In the latter half of the 20th century, microprocessors faithfully adhered to Moore’s law, the well-known formulation of exponentially improving performance. As Gordon Moore originally predicted in 1965, the density of transistors, clock speed, and power efficiency in microprocessors doubled approximately every 18 months for most of the past 60 years. Yet this trend began to languish over the last decade. A law known as Dennard scaling, which states that microprocessors would proportionally increase in performance while keeping their power consumption constant, has broken down since about 2006; the result has been a trade-off between speed and power efficiency. Although transistor densities have so far continued to grow exponentially, even that scaling will stagnate once device sizes reach their fundamental quantum limits in the next ten years. Due to this stagnation, processors, like those used for NASA’s navigation, communication, and telemetry systems, lack the scaling necessary to push space exploration further. A more energy efficient architecture/technology is required in order to increase the information bits per unit energy, and push processors architectures pass the thermal limits currently preventing increased speeds. Photonic integrated circuit (PIC) platforms provide a solution to this emerging challenge. PICs are becoming a key part of communication systems in data centers, where microelectronic compatibility and high-yield, low-cost manufacturing are crucial. Because of their integration, PICs can allow photonic processing at a scale impossible with discrete, bulky optical-fiber counterparts, and scalable, CMOS-compatible silicon-photonic systems are on the cusp of becoming a commercial reality. More specifically, Neuromorphic Photonics allow for the benefits of PICs to be merged with the benefits associated with non Von-Neumann processor architectures allowing for increases in both speed and energy efficiency.