An Innovative Additive Manufacturing Technology for High Density Interconnects

The goal of this phase I project is to evaluate and demonstrate the feasibility of fabricating high density interconnects and micro-bumps for high performance stacked chip detector instrumentation using an innovative additive manufacturing technology called confined electro-deposition (CED) printing developed during 2017. The Phase I work plan includes the following objectives: 1. Room temperature 3D additive printing of micron wide copper interconnects on silicon chip edges that can enable chip-to-chip & wafer-to-wafer interconnection and minimize dead regions at device edges. 2. Room temperature 3D additive printing of 10-20 micron diameter copper-core solder micro-bumps for high density vertical stacking of chips and wafers. 3. Characterization of adhesion, electrical and mechanical properties of 3D printed bumps and interconnects in relation to high density instrumentation requirements. 4. Development of standard operating procedures for 3D printing of micro-bumps and high density interconnects; including deposition rate calculations, techno-economic modeling and preliminary reliability/environmental testing. 5. Development of Phase II plans involving fabrication of a 3D printed high density multi-chip detector instrumentation in collaboration with NSCL at MSU, and a detector chip manufacturer. The advantages of the proposed technology include fine line pure copper interconnects (both vertical and horizontal) at room temperature without any need for masks, directly on chips and wafers; fabrication of high strength copper core to produce reliable solder micro-bumps in the sub 50 micron range for chip-to-chip & wafer-to-wafer stacking.