An Innovative Additive Manufacturing Technology for High Density Interconnects

The goal of this phase II project is to capitalize on the successes of the Phase I project for fabricating high density interconnects, thermal vias and micro-bumps for high performance stacked chip detector instrumentation using an innovative additive manufacturing technology called confined electro-deposition (CED) printing developed.The advantages of the proposed technology include fine line pure copper interconnects (both vertical and horizontal) at room temperature without any need for masks, directly on chips and wafers; fabrication of high strength copper core to produce reliable solder micro-bumps in the sub 50 micron range for chip-to-chip & wafer-to-wafer stacking.Phase I work experimentally demonstrated the following technical objectives: (i) 3D additive printing of high density copper interconnects on silicon chip edges that can enable chip-to-chip & wafer-to-wafer interconnection and minimize dead regions at device edges, and (ii) room temperature 3D additive printing of 10-20 micron diameter copper-core solder micro-bumps for high density vertical stacking of chips and wafers.During the proposed Phase II, the UHV team proposes to accomplish the following objectives: (i) complete & optimize 6 axis 3D printer for HDIs, thermal vias and microbumps, (ii) develop a micro-fabricated print-head for simultaneous printing of multiple bumps on a chip, (iii) fabricate and characterize 3D printed HDIs, thermal vias and microbumps, (iv) modeling, simulation, fabrication and testing of new 3D stacked chips, and (v) design, fabrication and testing of a low cost commercial printer for stacked 3D stacked chips.The multi-disciplinary proposing team includes subcontractor university of Texas at Dallas with expertise in 3D printing modeling and materials characterization, and two consultants with expertise in high performance silicon chip manufacturing and commercialization.