SBIR/STTR Research Award
Advanced Analog-to-Digital Converter for GPS Receivers
Award amount
$149,999Program and phase
SBIR · Phase IAward year
2017Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- SILICON TECHNOLOGIES, INC.
- Proposal award date
- 2017-08-18
- Contract end date
- 2018-05-18
- UEI
- SPL4KDQD5L49
- Solicitation number
- 2017.1
- Topic code
- AF171-128
Research abstract
The USAF is interested in this development for use in a digitally-processed GPS receiver with strong anti-jam performance. The focus of this effort will seek to develop an ADC architecture that can be built in a commercial CMOS foundry and achieve 350 MSPS and 16ENOB with minimal power and cost.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Radiation Hardened Data Converter Architecture in Intel Corp. 16 nm
- Data Converter Systems on Chip
- Data Converter Systems on Chip
- Lithography Cost Reduction for Rad Hard Integrated Circuits
- Speaker Driver and Wireless Transciever ASIC
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Advanced Analog-to-Digital Converter for GPS Receivers
- A 45nm SOI-CMOS 350 MSa/s 16b ADC with FPGA Digital Calibration
- Advanced Analog-to-Digital Converter for GPS Receivers
- Advanced Analog-to-Digital Converter for GPS Receivers
Research funding history
15 SBIR/STTR records share this UEI (2011–2022). Reported award amounts total $5,942,157. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration