Lithography Cost Reduction for Rad Hard Integrated Circuits

The DoD faces mounting costs for integrated circuits built with advanced technology. Our proposal addresses mixed-signal ASIC design costs and fabrication costs, notably photomask costs and photolithography costs. The ADONIS 1D design methodology has been demonstrated at technologies ranging from 130nm to 16nm. In Phase I of the program, we used ADONIS to design a reference circuit a high-speed comparator in 16nm FinFET technology. The design was then tuned for Complementary E-Beam Lithography. The result was a 34% reduction in the number of exposures needed by the CEBL system, which would translate directly into reduced patterning time. The comparator design was released for fabrication at 16nm through the DARPA CRAFT program. In Phase II we are proposing to extend the work to include 200 logic cells, an SRAM instance, 20 mixed-signal functional blocks, a DICE-like differential amplifier, analog and digital circuits to implement chip specific writing, and a high-performance analog front end. The comparator from Phase I will also be bench tested. A testchip will be designed to demonstrate compatibility with the CEBL equipment. Finally, we look forward to Phase III in which we can productize our work with a DoD contractor partner like Northrup Grumman (our prime