SBIR/STTR Research Award

Picosecond Timing Measurement IC for Particle Physics Experiments

Award identifier c89341b79899a9fe16173556a6ddeb87eb9c395bd0cdc4abe64265c3a8751d7fAwarding agency Department of Energy

Award amount

$154,947

Program and phase

SBIR · Phase I

Award year

2017

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
Alphacore, Inc.
Proposal award date
2017-06-12
Contract end date
2018-03-11
UEI
CXMPDDLFBCH3
Solicitation number
DE-FOA-0001619
Topic code
27j

Research abstract

Several high energy physics experiments require accurate timing measurements and transient digitization at high sampling rates, equaling or exceeding 10 gigasamples per second (GSPS). To date, only a few transient digitizer chips have been developed for this purpose and they are based on storing the analog samples onto long buffers from which they are digitized with low-rate analog-to-digital converters (ADC). These digitizers provide low power dissipation per channel but they suffer from limited buffer length, long latency between samples (microseconds) and high jitter (> few picoseconds). A low-jitter continuously sampling ADC would be a solution to the problems described above, but the only available COTS ADCs in the +10GSPS sampling rate range have way too low resolution (less than 4 bits) too high power dissipation (>4W) to be used in most of the experiments. In this SBIR program Alphacore, Inc. will develop a low-power, low-jitter ADC that has a sampling rate of 10GSPS. The advantages of this ADC are that it is continuous sampling which provides practically infinite sampling buffer depth, it has almost zero latency, jitter is below 100 femtoseconds and power dissipation is below 500mW. The ADC also provides seamless, ultra-high-speed interfacing to FPGAs (14.4Gb/s transceiver interface will be designed), which provides great benefits to system designers. The chip will be designed in a high-speed, low-power 28nm CMOS SOI technology that also provides inherent radiation hardness for total ionizing dose and single event effects. In Phase I Alphacore will design and simulate all the sub-circuits needed in the ADC. Alphacore aims to demonstrate the feasibility of the concept during Phase I, followed by fabrication and testing of a prototype in Phase II. Alphacore has received support letters from the U.S. collaboration members currently working on high-speed digitizer applications for CMS Totem upgrade and for ATLAS experiments requiring picosecond timing resolution. Alphacore has also received support letters from the Electron-Ion Collider collaboration and from Lightsource II, a new facility at Brookhaven National Laboratories providing an extremely high brightness x-ray source for basic energy science studies and requiring a rad- hard, gigasample digitizer that does not have any deadtime. Alphacore’s digitizer can also benefit many other applications, such as radio astronomy applications, radar and LIDAR applications, communications applications and high speed test equipment.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

155 SBIR/STTR records share this UEI (2013–2026). Reported award amounts total $63,784,604. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy, Department of Commerce

Agency intelligence

Department of Energy

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