Wafer-Level Electronic-Photonic Co-Packaging

To address the US Air Force need next-generation optoelectronic systems with heterogeneously integrated photonic and electronic components, Applied Optronics (AO) proposes to develop a Three-Dimensional Integrated Silicon Photonic Chip, which is based on a novel multilayer photonic architecture, enabled by interlayer optical coupling. The TISPIC architecture is compatible with silicon photonic and III-V active devices. The proposed technology will provide a flexible 3D platform for implementing significantly more complex photonic devices in a compact chip footprint, which is fully compatible with the current trends in high-density 3D electronics development. The TISPIC approach is also fully compatible with the CMOS fabrication process. In Phase I, we plan to demonstrate the feasibility of the proposed TISPIC technology via comprehensive system modeling and proof-of-concept laboratory experiments. We will also identify a preliminary chip design for prototype fabrication based on existing AOC customer requirements for testing in Phase II. We expect the TISPIC technology to reach Technology Readiness Level (TRL) 3 at the end of Phase I. During Phase II, we will further develop individual aspects of the TISPIC technology and demonstrate a TRL-5 packaged prototype.