Wafer-Level Electronic-Photonic Co-Packaging

In this STTR effort we will develop key packaging techniques for wafer-level hybrid electrical-optical co-packaging based on silicon photonic platform. These techniques include packaging LiNbO3 modulator on insulator (LNOI), high-speed modified uni-traveling carrier (MUTC) photodiodes packaging and high-efficiency fiber coupling. Silicon is the desired host material for photonic integrated circuits (PIC). However, key components such as modulator and photodiode made directly in silicon still cannot compete with the existing technologies. Hybrid wafer-level packaging technologies are therefore in urgent demand. In phase I, we will design and numerically study high efficient coupling structures between SOI waveguides and LNOI modulators or MUTC photodiodes through vertical stacking. We will develop the basic process flow and conduct the proof-of-concept demonstration for modulator and photodiode integration. We will collaborate with Dr. Zhaolin Lus in Rochester Institute of Technology in transitioning his high efficiency plasmonic coupler. In phase II, we will refine the packaging processes for improved device performance and process reliability. We will apply the developed packaging techniques to microwave photonic transmitter/receiver modules featuring LNOI modulators and MUTC photodiodes packaged on silicon platforms. PSI is poised to insert such devices to our existing DoD projects targeted at analog photonic link and broadband antenna array.