High-Sample-Rate Analog-to-Digital Converters

Thanks to the availability of downscaled CMOS devices, analog-to-digital converters (ADCs) implemented in these faster CMOS technologies have achieved increasingly efficient conversion rates in the GS/s range. However, given the reduced linear dynamic range, these scaled CMOS technology nodes require extensive calibration to compensate for transistor mismatch and threshold-level variations. This necessitates extensive digital signal processing, either on the ASIC or a companion FPGA chip. These factors contribute to what appears to be an imminent speed-resolution performance saturation in high-speed ADCs, as only modest progress is being made toward the thermodynamic sampling limits of the figure of merit used to describe ADC performance. To address this opportunity, a 40-GS/s ADC with at least six effective number of bits (ENOBs) will be developed. First, a trade study will be conducted, and a systematic design of a series of 40- to 80-GS/s ADCs, with 20-GHz to 40-GHz bandwidth, respectively, will be conducted.After the benefits of each are explored, a single design will be down-selected, and the critical track-and-hold amplifiers (THAs), sampling circuits, comparators, and clock distribution networks will be simulated and laid out. Performance of the extracted design will be verified to meet bandwidth and sampling requirements. The design will then be submitted to the foundry for fabrication. Then, key circuit components will be laid out, extracted, and verified, and the ADC submitted for fabrication.In Phase II, a series of fully functional 40-GS/s ADCs (80- GS/s objective) will be fabricated, fully characterized, and bandwidth and sampling capabilities verified.