SBIR/STTR Research Award

SBIR Phase I: Thin crystalline technologies for advanced power transistors

Award identifier 1b1ba98c1e7aa70f50d8332cd269fdd6028b5d212e37d04d224d6a5a08fd2549Awarding agency National Science Foundation

Award amount

$150,000

Program and phase

SBIR · Phase I

Award year

2016

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
APPLIED NOVEL DEVICES, INC.
Proposal award date
2016-01-01
Contract end date
2016-06-30
UEI
VZANADJA6MA4
Solicitation number
Not reported
Topic code
S

Research abstract

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to enable smaller chargers, power factor convertors and switches in applications ranging from small applications such as implanted pace-makers, mobile-phones, computer to large applications such as automobile, machinery to very large applications such as ships, locomotives, traditional and renewable energy power plants. While the impact of the power switching product to be developed using this technology in this phase II project is broad, the use of this thin crystalline technology can have even broader impact across all modern semiconductor devices such as LED, PV, flexible CMOS and passive devices. The project will potentially enable thin form-factor packages in this broad range of power electronics applications. This Small Business Innovation Research (SBIR) Phase I project addresses challenges to further scaling of power MOSFETs which are one of the key building blocks of the electronic revolution we have witnessed over the last few decades. While the feature size of transistors has been constantly shrinking, the substrate thickness has been increasing. These substrates are currently mechanically thinned to minimize the negative impact of this increased thickness on performance and form-factor. There are significant challenges to continue this trend and the thin crystalline technology and device architecture proposed here can enable continued scaling of device metrics over the next decade with favorable cost structures. This effort will focus on the following specific technical challenges to bring it to market. (1) Develop power MOSFETs with improved switching characteristics using the thin crystalline technology (2) Develop the process technology on large area wafers used in current production lines (3) Develop the low-form factor package using the metallization features of thin-crystalline exfoliated technology (4) Characterize the device for performance and insertion into high volume de-risk (5) Develop a roadmap for a family of products that is sustainable over a decade to justify significant manufacturing investment to bring this technology to market.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

9 SBIR/STTR records share this UEI (2014–2023). Reported award amounts total $4,765,210. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Science Foundation

Agency intelligence

National Science Foundation

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