Security Improvements for Field Programmable Gate Arrays (FPGAs)

In this Phase II SBIR project, The Athena Group, Inc., will develop an innovative technology to improve the security of field programmable gate arrays (FPGAs). This technology will be realized as a customizable intellectual property (IP) block that can be readily included in FPGA designs, will consume minimal hardware resources, and will have a negligible impact on the performance of the device. Besides improving the design security of FPGAs, the IP block will also provide security services for the end application, relieving the application designer from the costly and time consuming task of implementing these functions in a secure manner. As an IP block that can be included in the design of an FPGA, the costs and schedule risks of implementing enhanced FPGA design and application security will be dramatically reduced. Approved for Public Release 15-MDA-8169 (20 March 15)