SBIR Phase I: A Novel CMOS Device Architecture and Tools for beyond 14 nm Transistors

This Small Business Innovation Research (SBIR) Phase I project aims to demonstrate a innovative device architecture (UT-FET: Ultra Thin Field Effect Transistor) for scaling of FinFET devices beyond the 14nm node. The outcome of this project will be a CMOS device that is scalable and reduce off-state leakage as well as minimize threshold voltage variation. This project will develop a process technology that is compatible with high volume manufacturing using industrial toolsets. The main objective for the phase 1 of the proposed SBIR project is to demonstrate prototype UT-FET devices using manufacturing-capable tools and processes. The UT-FET device architecture involves a novel means of isolation of the device that can reduce cost, reduce leakage and increase speed of electronics systems. In this phase 1 of the SBIR project, production capable tools and processes will be used to demonstrate scalability of the technology for volume manufacturing. Successful completion of this technology demonstration can allow insertion of this technology into the growing markets for low power mobile communications electronics. The broader impact/commercial potential of this project will be address and overcome the current limits to scaling in low power electronic devices. Low power electronics devices use CMOS technologies and the scaling of these devices have been the driving force behind the communication revolution over the last two decades. Further scaling of these devices will enable faster communication, longer battery life and more energy efficient operation of electronics systems. Additionally in the process of developing and demonstrating this technology new scientific and technological understanding of using thin crystalline devices and the tools to manufacture them in high volume will enable other applications in energy, RF signal processing and power management.