Low Power Multi-Channel RF and Digital GPS Anti-Jam ASIC

ABSTRACT: There are numerous military applications where incorporation of Anti-Jam (AJ) GPS technology has been constrained by Size Weight and Power (SWaP), including handheld systems, unmanned aerial or ground vehicles, and munitions/weapons. The essential elements for incorporating AJ capability into GPS receivers are multi-channel RF front end down conversion, analog to digital conversion (ADC), and digital AJ processing. The goal of this program is to integrate multi-channel RF front-end and Digital AJ processing circuitry onto a single ASIC and interface this device with next generation military GPS receivers. RBS Technologies has formulated a Phase I effort that will define and assess architectures for the RF front end ASIC subsystem and the AJ digital processing ASIC subsystem that when combined into a single GPS AJ ASIC will be compatible with state of the art L1/L2 GPS modernized SWaP constrained receiver technology; be capable of accepting RF inputs from a 2-element (option of 4-element) CRPA simultaneously at L1 and L2 GPS frequencies, provide at least 30dB of anti-jam protection for up to 2 (option of 3) 24MHz wide Gaussian noise interference sources; successfully pass GPS M-code signals that can be used by modernized GPS receivers for navigation; and consume less than 1 watt. BENEFIT: The development of a microelectronic chip implementation for anti-jam GPS processing that will reduce size, weight, and power by a factor of ten has a very large market for resource constrained military applications, which include handheld systems, unmanned aerial or ground vehicles, and munitions/weapons. In addition, there is significant potential market for civilian law enforcement and homeland security. The microelectronic chip implementation will also be a candidate for replacing current technology for applications where size and power is not a constraint because the microelectronic implementation will have significantly lower cost and increased reliability.