EM Emanation Reduction Technique for FPGAs

This effort seeks to build upon our successful Phase I effort to utilize, refine, and perform detailed testing on designs utilizing our EM Emanation Reduction (EMER) technique for FPGAs. The EMER technique is designed to reduce the feasibility of side-channel attacks aimed at gaining critical program information in FPGAs used in BMDS assets, by making it substantially more difficult for an exploiter to reveal protected information via EM emanations from the FPGA. Due to the growing popularity of FPGAs and to the sensitive information programmed into them, it is important to find ways to safeguard the designs programmed into them from reverse engineering. Optimally, several layers of protection would be employed, so that even if an exploiter successfully penetrated one or more levels of protection, they would still find that the design was protected. The goal of this effort is to dramatically reduce the EM emanations from the FPGA, hiding the design from reverse engineering exploits using EM emanations. This technique has no external hardware requirements, making it suitable for co-integration with a variety of other AT/anti-reverse engineering approaches to thoroughly protect an FPGA.