SBIR/STTR Research Award

High-Speed High-Fidelity Reprogrammable Kernel for DRFM Applications

Award identifier 81dbaa1bc81e6e33d860ff8580c713a6186d656eb55fccf5fc2ada1136a6acf0Awarding agency Department of Defense · Navy

Award amount

$79,949

Program and phase

SBIR · Phase I

Award year

2012

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Award details

Awarding agency
Department of Defense
Branch
Navy
Recipient company
EUVIS
Proposal award date
2012-06-05
Contract end date
Not reported
UEI
CM2DR5QLNA33
Solicitation number
2012.1
Topic code
N121-034

Research abstract

A four channel DRFM module integrated the GHz ADC and DAC with Xilinx Vertex6 FPGA on the PCB is proposed. All the components will use proven commercial off-the-self (COTS) products to minimize technical risks. The converters will be selected based on the bandwidth, broadband SFDR, latencies and synchronization capabilities. DSP core is propsoed with polyphase channelized receiver and transmitter for single signal path.The basic amplitude, phase and frequency modulations will be implemneted with frequency resolution better than 0.1 Hz. Three types of memories will be used to meet the delay and data size requirements. There will be four signal paths for a complete DRFM kernel. This DRFM module leverages the core technologies of Euvis'existing module products such as Multi-Gsps AWGs, 2 Gsps digitzers and FPGA codes. The developed DRFM will provide 500 MHz instantaeous bandwidth with 60 dB SFDR.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

6 SBIR/STTR records share this UEI (2005–2012). Reported award amounts total $1,844,945. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense

Agency intelligence

Department of Defense

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