Backend Error-Correction Algorithm Unit for Superconducting ADCs

Physical Optics Corporation (POC) proposes, in Phase II, to mature the first-of-its-kind Backend Error Correction Algorithms Unit for Superconducting ADCs (BECAUS), developed and proven feasible in Phase I. To date, POC has demonstrated a 2.5-bit improvement in the effective dynamic range of a superconducting ADC with a TRL-3 proof-of-concept prototype, which places the error-corrected ADC at a competitive advantage with respect to the state-of-the-art. In Phase II, insight gained from an extensive investigation into the unique errors associated with superconducting ADCs will be applied to optimization of the error-correction codes. Real-time hardware prototypes incorporating these algorithms will be developed in a two-step process. The first-generation BECAUS prototype, based on off-the-shelf field programmable gate array (FPGA) technology, will be capable of backend error correction of signal bandwidths up to 700 MHz, and input data rates up to 32 Gbps. The second-generation prototype, based on a custom application-specific integrated circuit (ASIC), will extend the signal bandwidth capability to over 10 GHz, with input data rates exceeding 160 Gbps. POC will collaborate with the leading manufacturer of superconducting ADCs for this effort, ensuring a timely transition of the BECAUS technology to Navy software-defined receiver applications.