Automated Generation of Advanced Test Diagrams to Reduce Test Program Set Life-Cycle Costs

The objective of this Phase II research project is to develop a process and associated tools to generate wiring test diagrams automatically using data compliant with the IEEE Automatic Test Markup Language (ATML) family of standards. Test diagrams show the routing of signals from instruments to Unit Under Test (UUT) pins for each test in an automatic test program which tests a UUT on an Automatic Test Equipment (ATE) and are extremely useful in the troubleshooting of a Test Program Set (TPS). Automating the test diagram generation process will decrease the lengthy time to generate test diagrams by eliminating many hours of analysis of test stations, test programs and associated interface hardware. The Phase I study identified methods to use ATML data to generate test diagrams which provides a much desired open systems approach and will be employed in Phase II. Phase II work will also consist of producing ATML development tools for the ATML Test Station and Test Adapter to assist in the generation of ATML instance files, the resultant files will be used as an input to the test diagram tool. Phase I demonstrated that ATML support tools are essential for cost effective implementation of the ATML standards.