Automated Generation of Advanced Test Diagrams to Reduce Test Program Set Life-Cycle Costs

The objective of this proposal and the proposed research project is to investigate the feasibility of developing a process and associated tools to generate wiring test diagrams automatically using data compliant with the Institute of Electrical and Electronics Engineers (IEEE) Automatic Test Markup Language (ATML) family of standards. Test diagrams show the routing of signals for each test in an automatic test program which tests a Unit Under Test (UUT) from an avionics system or other weapon system on an Automatic Test Equipment (ATE). The test diagrams provide the complete routing of signals from test station instruments to UUT and are a key support document, useful throughout the life cycle of the Test Program Set (TPS). Automated processes for test diagram generation promise to decrease the lengthy time to generate them by eliminating many hours of analysis of test stations, test programs and associated interface hardware. The proposed solution should also enhance the update process and eliminate errors and inconsistencies typical of manually generated diagrams. Relying on the ATML standards for the format of data in this process is a key component of this proposal and will provide a much desired open systems approach.