SBIR/STTR Research Award

High Productivity, Robust FPGA Programming Tool

Award identifier 166e3ca33161f7f43026537ad3b30e6d608a0fb6b1462e4be80d66c9c3ad9e95Awarding agency Department of Defense · Navy

Award amount

$148,250

Program and phase

SBIR · Phase I

Award year

2011

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Award details

Awarding agency
Department of Defense
Branch
Navy
Recipient company
Dsplogic Inc
Proposal award date
2011-05-02
Contract end date
Not reported
UEI
R71SN7GNMT58
Solicitation number
2011.1
Topic code
N111-014

Research abstract

Field Programmable Gate Arrays (FPGA) are a very attractive, and often necessary, computational resource for intensive Digital Signal Processing (DSP) applications, including guidance systems. Their balance of performance, power consumption, and size make them ideally suited to SWAP-constrained sensor, communication, and guidance applications. However, the lengthy FPGA development and validation cycle, combined with limited application portability, contribute to relatively high life-cycle costs compared to modern embedded software systems. We propose the development of a high-level graphical programming environment for FPGA-based DSP applications. This model-based design environment, based upon object-oriented hardware design principles, will facilitate rapid FPGA system design by algorithm engineers across multiple platforms. Support for rapid integration and re-use of Intellectual Property (IP) cores is central to the proposed effort.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

10 SBIR/STTR records share this UEI (2004–2018). Reported award amounts total $3,037,547. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense

Agency intelligence

Department of Defense

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