High Productivity, Robust FPGA Programming Tool
Award amount
$148,250Program and phase
SBIR · Phase IAward year
2011Award details
- Awarding agency
- Department of Defense
- Branch
- Navy
- Recipient company
- Dsplogic Inc
- Proposal award date
- 2011-05-02
- Contract end date
- Not reported
- UEI
- R71SN7GNMT58
- Solicitation number
- 2011.1
- Topic code
- N111-014
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Innovative Interconnectivity and Scheduling of Smart Sensors and Actuators for Reliable Propulsion Systems Controls
- Driver Performance Monitoring through Electronic Trip Tickets
- Programming New Computers
- Direct Detection Ladar Pulse Processing
- High Productivity, Robust FPGA Programming Tool
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- A Simulink-Based Design Tool for Mapping Guidance Algorithms into Field Programmable Gate Arrays
- Field Programmable Gate Array (FPGA) Direct Programming Tool
Research funding history
10 SBIR/STTR records share this UEI (2004–2018). Reported award amounts total $3,037,547. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense