Advanced Integrated Circuit Anti-Tamper Methods (configurable AT focus)

Tiger"s Lair proposes to research and develop a method of constructing a trusted chip design (ASSP, ASIC, FPGA) where the designer uses automated design tools and lightweight reconfigurable instruments (hardware IP) to create a fabric of embedded real-time security monitors and countermeasure functions that can be inserted into digital subsystems such as processors, memories, buses, peripherals, controllers, power management circuits, clock management circuit and legacy circuits to protect the chip from tampering, reverse-engineering, malware, Trojans and unauthorized use. A primary objective is to create reconfigurable instruments that will be very small and have minimal impact on the gate-count, area and system performance. Another primary objective is to create automated IP insertion tools that enable easy creation, configuration and insertion of instruments into specific areas of the design without requiring the user to have intimate knowledge of the hardware design. The use of design analysis and automation tools enables instrumentation IP to be"mixed and matched", and subsequently tailored to the specific application. The automation tools will also enable the automated insertion of third-party IP such that heterogeneous AT sensors can be integrated in silicon and general managed within the development process. BENEFIT: Using a combination of design tools and lightweight reconfigurable hardware IP we will enable protection of both new and existing products. This tool-based approach allows organizations to take control over all IP and establish standardized methods for security IP use and re-use based on correct by construction design automation techniques. The tools will provide substantial benefits to obsolescence management, technical refresh programs and retrofitting activities. The lightweight nature of the hardware IP allows protection to be added to systems with severe area or performance limitations, as well as legacy systems and proprietary circuits that cannot be protected using current large/intrusive security IP solutions. The proposed delivery method allows quicker adoption and standardization of embedded IP security solutions, and importantly, the potential to retrofit existing FPGA based systems with proposed protection schemes. The reconfigurable IP is technology agnostic, can be used in ASSPs, ASICs and FPGAs. It is transportable between any programmable logic devices. Tiger"s Lair will work in partnership with Raytheon to analyze the feasibility and practicality of retrofitting this technology into existing systems. Upon successful completion of Phase I, we will implement and demonstrate the proposed security scheme on an existing Raytheon system in Phase II.