Quantitative Back-Annotation of Simulink Models for Hardware Synthesis Optimization

Model Based Design and Implementation (MBDI) is an attractive alternative for FPGA development for several reasons: 1) Many Subject Matter Experts (SME) are already familiar with MBD environments for designing and validating algorithms, 2) the visual, data-flow oriented nature of MBD make it easy to describe highly parallel algorithms, 3) design automation eliminates traditional design, code, unit test and implementation phases, and 4) there is less risk of system design being “lost in translation” or errors being introduced in later design phases. The primary difficulties with MBDI are design optimization and validation. The SME must be able to optimize FPGA design tradeoffs, such as power, resource utilization and clock speed. Second, there must be a reliable method to validate bit- and cycle-accurate FPGA operation. Both of these tasks are made more difficult by the various stages of design representation, and hierarchical flattening that take place in the design flow. In order to optimize and validate the design, the SME must be able to clearly visualize and simulate the implemented design at all abstract representation levels, including the final implementation. This requires the output of the FPGA implementation tools to be back-annotated and linked to the Model in an intuitive way that is easy for the SME to understand. The primary goal of this project is to create a tool to solve this problem, allowing the optimized model developed by the SME to be the design for the final, fully validated implementation