Improved Dynamic Range ADCs

This proposal presents an Improved Dynamic Range ADC methodology that addresses key limitations in current ADC technology with respect to signal-to-noise ratio (SNR) and output bandwidth. This proposal leverages existing designs and technology already developed by OmniPhase, and scheduled for commercialization by 2010. The existing OmniPhase design employs proprietary ADC processing to attain extremely high SNR and SFDR performance across the full output bandwidth, providing a spurious-free dynamic range (SFDR) specification of 80 dB. It also supports downconversion and decimation with programmable bandwidth of 10 kHz to 300 MHz and decimated sample rates of 100 KSPS to 400 MSPS over an input RF bandwidth of DC to 2.6 GHz. The existing design is modified to utilize a novel ADC approach to improve SNR performance to provide a SNR of 82 dB at a 500 MHz output bandwidth, and 100 dB at a 10 MHz output bandwidth. The modified design provides 13.3 Effective Bits at 500 MHz output bandwidth, and 16.3 Effective Bits at a 10 MHz output bandwidth. An additional ADC circuit and post-processing digital downconversion (DDC) path are added to the existing design to provide a 600 MHz output instantaneous bandwidth.