Multi-input Synchronous Digital-RF Receiver

The goal of this project is to develop a digital-RF receiver system to enable direct digital reception from a SIGINT antenna array. In Phase I, we designed a two-input prototype chip integrating two oversampled delta ADCs with a common clock source, and two on-chip digital decimation filters. In Phase II, we propose to design, build, demonstrate, and deliver a complete cryocooled system with a dual-ADC chip. HYPRES demonstrated the first cryocooled ADC chip in SPAWAR Systems Center in November 2005. Since then, four improved system demonstrators have been delivered to Army, Air Force and Navy, representing 2x circuit complexity, 2.5x increase in clock speed (up to 30 GHz), and over 2x compaction in overall system size. Building on this platform, our proposed system will incorporate an elevated temperature stage for hosting multiple higher-temperature electronics modules, in addition to the dual-ADC. This is a significant step towards realization our hybrid-temperature, heterogeneous technology (HTHT) system concept, where various electronic and photonic technologies are integrated at temperatures ranging from 4 K to 300 K. Modular construction of the proposed HTHT system will ensure future upgrades with higher performance and more complex chips with minimum additional expense.