SBIR/STTR Research Award

Reliable and Rad-Hard Microelectronics

Award identifier fa4043321c01caf115ea49777be8583066e809c670e8dbb02d8a558232755f1bAwarding agency Department of Defense · Air Force

Award amount

$99,984

Program and phase

SBIR · Phase I

Award year

2009

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
RIDGETOP GROUP INC
Proposal award date
2009-02-25
Contract end date
2010-02-25
UEI
CRLUWHJZHLU8
Solicitation number
2008.3
Topic code
AF083-197

Research abstract

The ability to measure and characterize critical circuit parameters is a necessary requirement to developing reliable microelectronics for military applications. An industry-first capability is provided: a set of radiation-hardened by design (RHBD) test structures to allow design engineers to measure and characterize these critical parameters both before and after irradiation. Upon completion, these RHBD structures will be added to Ridgetop Groups Design-for-Manufacturing Tools (nanoDFM). Die Level Process Monitor (DLPM) are precise in-situ integrated circuits (ICs) placed onto a die to extract information that measure and characterize key parameters that are very susceptible to manufacturing process variations. Design engineers can then correct for process variations, better center designs, or adaptively correct operation as the IC degrades or becomes irradiated.  The DLPM structures are the following: (1) threshold voltage shift, (2) resistance mismatch and (3) capacitance mismatch. There are prognostic cells to detect radiation-induced voltage shifts, increased leakage current and memory cell errors. New structures provide information on Negative Bias Temperature Instability (NBTI) and the effects of process variation and radiation on timings and operations associated gates, voltage references and flip-flop memory cells. These structures will be designed for the IBM 65-nm 10RF bulk Complementary Metal Oxide Semiconductor (CMOS) process node. BENEFIT: Ridgetop Group owns patented DLPM and PDKChek technologies that have been successfully developed and used for larger feature size technologies.  For the smaller and lower-power IBM 65-nm 10RF bulk CMOS process, the existing DLPM and the new structures need to be designed, fabricated, tested and documented to provide design engineers with the necessary capability for extracting information to measure and characterize critical circuit parameters, which in turn leads to more reliable microelectronics: circuit designs can be more effectively centered. Radiation-hardened circuit designers will be able to extract the same level of information from a RHBD nanoDFM suite of tools: this is an industry-first capability.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

80 SBIR/STTR records share this UEI (2001–2025). Reported award amounts total $27,524,868. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

Department of Defense

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