Reliable and Rad-Hard Microelectronics

Producing components that satisfy all of the BMDS space and interceptor environment specs traditionally has been not only costly but also untimely.  As semiconductor companies continue along path set by Moores Law producing chips that have the necessary lifetime of a MIL Space application is a matter of fact.  Testing must be preformed on the silicon to ensure that the silicon will meet or exceed the extreme environments of space.  We propose in the Phase I test circuits that will enhance the reliability and the radiation hardness of the process.  On-chip metrology circuits will be designed to reduce test time and simplify the test setup. BENEFIT: If a Phase II and Phase III options are exercised for this proposal the AFRL and other DoD systems will have access to state of the art on-chip metrology circuits for monitoring the reliability radiation hardness of the Structured ASIC wafers.  Micro-RDC will be able to pre-screen Structured ASIC die quickly before they are sent of for full P&Q.  Micro-RDC will also be able to collect an extensive history of the process on a lot to lot bias.  These metrology circuits will not be limited to the 90 nm Structured ASIC fabric but will be useful in qualification of many technologies nodes.