Coherently Synchronized Distributed Signal Generation

Nu-Trek and Raytheon will develop a Clock Delay Adjust ASIC with a revolutionary digital phase adjust architecture. ASIC will include clock generation at frequencies > 20 GHz; sub-ps synchronization over distances up to 1 m; better than -90 dBc/Hz phase noise at a 100 kHz offset; correction of up to 50 ps of skew; for systems with up to thousands of channels. Key innovation includes: (1) Revolutionary digital phase-adjust architecture based on Linder cells. (2) Self-corrects for aging, temperature, and mechanical stress. Feedback circuitry provides the phase drift information to the Linder cell, which re-synchronizes the channels. (3) Large number of distributed, low phase noise, clock paths are implemented on the same integrated circuit as the digital delay adjustment electronics. (4) Each channel is calibrated individually, including per/channel propagation delay compensation. In Phase I we will simulate the Linder cell, phase detector, charge pump, and loop filter and demonstrate the feasibility of digitally adjusting the phase delay of very high speed (20 GHz), very low phase noise clocks. ASIC will revolutionize the size, weight, and cost of the antenna array electronics and is directly applicable to a number of DARPA programs including ISAT and ISIS.