Deep Submicron Radiation Hardened Logic for Communications

Micro-RDC will investigate scaling our 90nm Design-Hardened Structured ASIC (DH SASIC) to deep submicron (65nm, with considerations towards 45nm) feature sizes, enabling the design and fabrication of high-performance digital integrated circuits for satellite communications systems, especially for Transformational Satellites (TSATs).  To make our planned DH ASICs affordable we will design a family of base arrays on a Multi-Project-Wafer (MPW) reticle that are single reticle Via-layer programmable, for fabrication at a trusted foundry. These concepts enable cost sharing with other designs on the same reticle.  We also plan to design a lot qualification coupon on our reticle so that flight-level silicon qualification of all designs on the reticle can be accomplished on a lot basis, providing flight-silicon qualification cost sharing with other designs on the same reticle. During the Phase I program Micro-RDC will identify the performance characteristics of a 65nm DH SASIC, investigate reliability risks associated with scaling, identify any radiation hardness concerns regarding our existing design-hardened cell/macro library, identify the extent of any software revisions needed regarding the development of a 65nm DH SASIC, investigate macro functions needed by communications satellite IC designers and then propose a family of 65nm DH SASIC base arrays appropriate for Single Reticle-MPW fabrication. BENEFIT: This effort will investigate the feasibility of developing a deep-submicron (65nm, with considerations for 45nm) Design-Hardened Structured ASIC technology.  Due to the novel concepts envisioned for fabrication, it is a very affordable design vehicle, making it useful for many applications and markets, from commercial IC prototyping to the development of high-performance flight-qualified design-hardened integrated circuits for military and aerospace applications. IC designers will find it to be a preferred platform, especially for complex designs that require more than one design iteration.