Exploiting Commercial Microelectronics for Space Applications

State-of-the-art integrated circuit serializer/deserializers (SERDES) produced at 90nm geometries and below have identified Single Event Effect (SEE) hardness weaknesses, especially Single Event Transient (SET) induced multiple bit data loss in high speed data paths.  MRDC will address these effects in Phase I through application of our extensive design hardening experience to a >4Gbps SERDES macro by hardening all components required for a SEE hard high data rate SERDES.  We will evaluate the SEE hardness level of an existing MRDC PLL and the high speed differential cells needed to process very high rate data streams for applications in fiber channel and XAUI systems.  We will propose improvements in circuit topologies which will demonstrate a significant increase in SEE hardness of the PLL and the high speed data path over current standard implementations.  During these analyses any other circuit modifications to improve the SEE hardness of the overall SERDES design will also be implemented.  The Phase II effort will be sequential to Phase I and result in a fully SEE hard SERDES interface capable of supporting 4Gbps fiber channel interfaces being built in a <90nm state of the art CMOS process based on existing intellectual property of MRDC and fully characterized for use in radiation environments. BENEFIT: This technology will enable high data rate communications for the space community for the first time.  By doubling to quadrupling the data transfer rate available current bottlenecks in high bandwidth communications will have a solution.  Commercial applications include 4Gbps and 8Gbps Fiber Channel, XAUI, SAS, and any other serial data transfer protocols which require a high bandwidth SERDES.