SBIR/STTR Research Award

Highly Scalable Readout Integrated Circuit (ROIC) with Thermal Image Processor Chip to Support the 12um SXGA Microbolometer on Glass Development Effort

Award identifier d952b58aed28ffb04cc866ec147f4c528748ef15b0ba9ae3a750e5eb846d7991Awarding agency Department of Defense · Army

Award amount

$1,998,549

Program and phase

SBIR · Phase II

Award year

2025

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
OBSIDIAN SENSORS INC
Proposal award date
2025-08-15
Contract end date
2027-02-25
UEI
MJ31DS67J377
Solicitation number
24.4
Topic code
A244-024

Research abstract

Obsidian Sensors' microbolometers on glass technology is a proven platform that combines a highly scalable focal plane solution with an unmatched manufacturing solution that addresses the cost and scale barrier that has prevented wider adoption across the dual-use landscape. The adoption of a new substrate with a low-cost flat panel glass manufacturing infrastructure has led to the introduction of a VGA class uncooled microbolometer product that is already being shipped to both commercial and defense customers.  Obsidian’s focal plane architecture is distinct from conventional approaches with performance, yield, scalability advantages that result from two distinct components combined at the backend packaging phase: a glass sensor panel that comprises the pixel array with integrated backplane and a CMOS chip that implements the readout function.  Our use of the term ROIC refers to this limited sense whereas the conventional ROIC is the monolithic combination of both backplane and readout functions.To support the development and build of a SXGA (1280x1024) resolution microbolometer, this project aims to design and develop a ROIC that combines several important functions: 1) readout of pixel data to yield digital pixel output values at a rate of 60 frames per second, 2) integration of NUC (non-uniformity correction) as well as an efficient image processing pipeline to yield high quality images and video output, 3) a secure authentication capability to lock the use of the device to authorized hosts. The Phase 1 effort was a system design effort that examined various options including the question of whether to use a single chip or two chip solution for the combined ROIC and ISP (image signal processing) functions, as well as the CMOS technology node most relevant for the development effort.   With an anticipated sequential Phase 2, the project will deliver what we call Palomar 2, a fully integrated ROIC with ISP for use with the SXGA glass panel to be developed and delivered under another SBIR effort underway.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

9 SBIR/STTR records share this UEI (2020–2025). Reported award amounts total $7,347,162. Reported amounts are not federal obligations.

Phases: Phase II, Phase I, Phase II – Direct to Phase II

Agencies: National Aeronautics and Space Administration, Department of Defense, National Science Foundation

Agency intelligence

Department of Defense

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