Highly Scalable Readout Integrated Circuit (ROIC) and Thermal Image Processor Chip to Support the 12um SXGA Microbolometer on Glass Development Effort

Obsidian Sensors has established a completely new approach to building uncooled microbolometers, on glass substrates not Silicon and built in a standard flat panel display foundry, not a specialty Si MEMS fab.  The advantages are twofold, 10X lower costs and 100X greater scale in terms of the ability to source more than 100M units per year.  Obsidian is already delivering focal plane arrays and cameras built with this new technology and an exciting effort is underway to improve the manufacturing process to support a 12um pixel pitch (currently 24um).  Central to the new microbolometer on glass paradigm is a unique ROIC architecture which is no longer monolithically integrated into the focal plane array.  The ROIC as a separate chip that is combined with the focal plane using a hihgly reliable and low cost flex on glass bonding technology is already being delivered to customers.   The proposed effort is a vast improvement to the current capability, aiming to reach the important SXGA (1280x1024) resolution format and beyond as quickly as possible.   Palomar 2 is the name of the new ROIC which will feature the ability to address up to 1344 channcels (columns) of sensors simultaneously with 60Hz frame rate capability for up to 1024 rows (lines).   The current ROIC Palomar 1 has 648 channels and can support 30Hz up to 800 rows.   Additionally, we propose an accompanying chip that we are calling a Thermal Image Processor.  The algorithmic basis for this chip has already been proven out in FPGA firmware using a small 40K LUT (look up table) Lattice chip, featuring a 2 point NUC (non uniformity correction) block, an ISP (image signal processor) block, multiple MIPI input and output interfaces and a unqiue security feature to lock the use of the Palomar 2 ROIC with an authorized TIP.   The Phase 1 effort will result in a complete system requirements document as well as the detailed analog design of the higher order sigma delta conversion circuitry that is another key improvement over Palomar 1.   The follow on Phase 2 efforts will lead to silicon that will demonstrate the key features of the chip set.