Ultra-Dense Three-Dimensional Electronics for Space

Chip-to-chip I/O has become a serious bottleneck, especially in communications between high-speed processors and their memory devices. Integrating a large amount of memory and a powerful processor into a single 3D-IC device could alleviate this problem. Bringing the memory on-chip with a very wide bus and very short vertical interconnects would greatly increase the speed and frequency of I/O between the processor and memory. Designing and optimizing such a device would be a large and expensive undertaking. The proposed program looks to examine the 3D solution in a limited scenario, making minimal changes to an existing memory design and an existing CPU. This will not fully exploit the huge performance benefits of 3D CPU+memory integration, but it will provide a valuable proof-of-concept for future work. BENEFIT: The benefit of this project will be the demostration of technology that will fundamentally change the way compute engines are designed. The provision of large fast memories that function as a direct extension of the data processing silicon has direct commercial application and indeed will enable the next major stride in data processing.