Production Enhancements for Integrated Anti-Tamper Technologies

The primary objective of this Phase I program will be to demonstrate a greatly improved manufacturing and production techniques for die packaging of anti-tamper capabilities. We aim to show through manufacture engineering research, software development and hardware prototypes, a new low-cost technique for multi-threat capable Anti-Tamper (AT) device manufacture and AT software-based multi-threat Die production packaging that will reduce the present risks associated with direct hardware AT integration with a range of security critical devices (such as FPGA, ASIC, memory and RF die wafers). Being guided by an MDA prime contractor/end-use integrator of the technology will substantially focus the efforts and improve chances for successful integration of protective techniques/technologies into several key MDA missions that are ongoing. The results will be largely applicable to many forms and types of hardware AT device packaging.