Design-Hardened Radiation Tolerant Microelectronics

This proposal describes an innovative radiation hardened by design approach for improving integrated circuit reliability while minimizing impact on area overhead, power consumption, and electrical performance degradation over indigenous libraries. The approach is based on an innovative built in current sensor (BICS) technique designed to provide portability across alternative foundries, newly developed processes, and diverse combinational and sequential digital, analog, and mixed signal design architectures including full custom, semi custom, standard cell, and programmable array integrated circuits. The BICS approach will be characterized and validated against a standard set of metrics, including design, area overhead, performance, and power consumption, and will determine its efficacy within a system integration recovery (SIR) environment developed by L3, our DEC teammate. Phase I will include simulation and modeling of feasible designs, process variations, subthreshold leakage, radiation effects, and reliability monitor. Design portability will be investigated for digital/analog full custom, semi custom, standard cell, and programmable array architectures. These results will become the baseline research for a transition into a Phase II contract. With the effective modeling and simulation approach conducted in Phase I, the Phase II project will develop the detailed design, fabricate and validate the BICS solution set.