Advanced IC Design Techniques for the Prevention of Reverse Engineering of the Programmed Functionality in FPGAs

Military and space-application FPGAs are invaluable for improving defense capabilities and deployment schedules; however, they also create a potential vulnerability if their configuration code can be discerned or if they can be directly used in unauthorized systems. Modern IC debug and repair techniques, such as PICA and FIB, represent formidable attack tools, which when combined with other attack strategies (such as electromagnetic [EM], power analysis [PA], and Power-Cycling) and sufficient time could defeat present-day FPGA security systems. This Phase 2 STTR effort will create novel circuits and procedures that realize FPGA security features that defeat the above attack strategies, protect the FPGA configuration store, and render the device unusable by a potential aggressor. Robust encryption techniques will protect the FPGA configuration code and IO paths from discernment by unauthorized users. Each IC will be programmed with unique hardware keys that can only be reverse engineered destructively. A defense-in-depth strategy includes robust symmetric encryption circuits that are immune to EM, PA, and LVP and PICA optical probing. Distributed attack detection circuits and IC disabling circuits will defeat exhaustive key searches and power-cycling.