Algorithm Development for Reconfigurable Computing Architectures

High performance reconfigurable computing (HPRC) is an expanding technology offering workstations and small clusters performance levels previously reserved for large-scale systems populating the "Supercomputing 500" list. However, the lack of open-source libraries of generically applicable numeric methods (i.e. BLAS, LAPACK, Numeric Recipes, etc.) optimized for FPGA embodiment has hindered adoption of HPRC by mainstream technical/scientific computing users. MNB Technologies and our academic partner, The Ohio State University, will simplify the HPRC development model. The approach has four thrust areas: 1) partially automating the process of developing HPRC optimized HDL from symbolic math, 2) extending HDL customization capabilities enabling hierarchical modeling using generic cores automatically customized for the target platform, 3) creation of a standard modeling and validation framework for quick and economical population of the library by the open source community, and 4) creation of a model integration tool "plug-in" for common application development environments. This approach provides an open-source use model for disadvantaged users and considerable commercialization opportunities for proprietary extensions to service both the HPRC and EDA (electronic design automation) market segments.