Algorithm Development for Reconfigurable Computing Architectures

Partial Differential Equations (PDEs) are at the core of Air Force scientific priorities in air vehicle design. The goal of this STTR is to provide unprecedent computational power to the solution of large-scale PDE problems in 3D through the use of reconfigurable computing linear equation solvers based on iterative methods. The result of this research will be packaged in a system that, by the end of Phase II, will be at least 1,000 times faster than commodity processors for the solution of PDEs. Four mission-critical areas to the success of FPGA-based solvers are identified: portability; ease of use; algorithmic speed balance between von-Neumann and non-von-Neumann components; and communication speed. Though particular innovations will be done in each mission critical area, special emphasis will be done in algorithmic speed balance, and PDE solvers based on mathematically successful iterative methods like Conjugate Gradient. By the end of Phase I there will be a prototype of the PDE solver, suited to solve 3D problems. Phase I will also deliver a clear technology roadmap in terms of algorithmic and architectural innovations needed to bring this project to success by the end of Phase II.