SBIR/STTR Research Award

Dual Chip Approach to Radiation Hardened Logic

Award identifier 5349fa8d2575a363881c79d79bd2396baad15dced8c632eb6d2072cad3727abeAwarding agency Department of Defense · Air Force

Award amount

$1,490,520

Program and phase

SBIR · Phase II

Award year

2007

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
MICROELECTRONICS RESEARCH DEVELOPMENT CORPORATION
Proposal award date
2007-06-11
Contract end date
2010-09-10
UEI
M2WCCD39B593
Solicitation number
2006.1
Topic code
AF06-256

Research abstract

In an electronics system, the incorporation of reprogrammable logic, such as Field Programmable Gate Arrays (FPGAs), into the design can offer many benefits to a digital designer. For radiation hardened reprogrammable electronics, the choices among appropriate devices are very limited. AFRL is at the forefront of designing and developing high performance radiation hardened digital solutions. One such solution is the Via Programmable Gate Array (VPGA), which offers designers the high performance offered by a deep-submicron (90 nm) process, and the flexibility of reprogrammability with only one mask layer change. However, for a design engineer accustomed to working with COTS FPGAs engineers, the path to implementing the design into the VPGA is not trivial. A design methodology is proposed to ease this migration. This design approach will facilitate the transferal of FPGA designs to VPGA designs. As an option to this proposal, we offer to design, manufacture, and test four flight designs crucial to the development of the Plug-n-Play Satellite (PnPSat). Because these designs are predominantly FPGA based, the option can serve as a springboard to VPGA implementations of these designs.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Agency intelligence

Department of Defense

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