Embeddable Software Programmable Radio

The goal of this project is to produce a chipset, composed of commercially available components, which can take advantage of the JTRS software communications architecture (SCA) and software waveform library. Because of the need for this device to operate at both unclassified and SECRET classification levels on a single processor, with a single operating system, a major focus of this effort will be to devise verifiable partitioning methods to prevent intermingling of differently classified information. NAVSYS has proposed a design for a Mini-SDR that uses COTS components and a partitioned design to significantly reduce the numbers of component needed to perform the red, black and crypto processing required for running a JTRS waveform. Under Phase I we propose to develop the Mini-SDR design and work with NSA to evaluate the security architecture against the Uniform Infosec Criteria. The Phase I design will result in a proposed Phase II effort to build a compact software programmable military radio chipset that is capable of being embedded in unitary computing, display and position location devices envisioned for future Marine Corps ground forces. We will provide supporting material for the design to predict the size, weight, cost and power of this embedded SDR solution.