SBIR/STTR Research Award

Coherent Clocking in Digital Arrays

Award identifier bd42b0ab427abe2b9b2dd470680e975a975b351476572708ba81a45cc06197f6Awarding agency Department of Defense · Navy

Award amount

$69,943

Program and phase

SBIR · Phase I

Award year

2006

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Award details

Awarding agency
Department of Defense
Branch
Navy
Recipient company
MHI Consulting LLC
Proposal award date
2006-11-02
Contract end date
2007-08-02
UEI
Not reported
Solicitation number
2006.2
Topic code
N06-164

Research abstract

We propose to solve the multi-point coherent-sampling problem in this solicitation by using our new clock distribution technology. Invented for multi-GHz VLSI clocking and beam-steering antenna array synchronization, our technique has substantially lower cost, lower power, better phase precision (skew) at the delivery points, and lower jitter than conventional corporate feed distribution systems. In addition, it is fully compatible with conformal applications, since it does not require any spatial uniformity or symmetries for proper operation, unlike tree networks. We use a serial architecture with transmission line connectivity between clients and a simple signaling method, which carries absolute timing information to any place along the chain. Not only that our method is capable of inexpensively and accurately distributing a high frequency clock signal but in certain implementations it delivers synchronous signals to the clients at twice the transmitted frequency. At the client points, we extract the absolute timing information with simple, classical circuits. In the case of sampling arrays, we have the capability of distributing a very high frequency sampling clock, which would be used directly by the client samplers without the need for local frequency multiplication for optimum jitter performance.

Technology keywords

Not reported

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Agency intelligence

Department of Defense

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