Array Clocking with Reduced Jitter Using Taped Delay Lines

Deriving coherent antenna array clocks from a common tapped delay line driven by a synchronizing pulse per clock cycle results in reduced jitter and optimal beam forming at minimal cost. Phase one effort analytically considers both electronic and optical implementations with an option for simulation-based validation of a critical PLL circuit and other physical parameters. Analysis considers three clock configurations: 1Ghz with 100FS aperature jitter (per RFP), 21Ghz (2 times X-band) with 50FS jitter and 40GHz (2 times low end of K-band) with 10FS jitter.