Secure Memory for Anti-Tamper (AT) Application

This SBIR Phase 1 project proposes the feasibility study of an integrated secure memory architecture for storage of critical software code such as encryption keys; capable of securely, quickly and reliably erasing that code in a minimal or no-power state in the event of tamper or directed destruction. In a tactical or time critical situation, conventional memory wipe processes are too lengthy to complete. A better alternative to overwriting clear memory to an acceptable randomness is needed. It must leave memory effectively in a random state, and execute completely in milliseconds. A valid approach for these objectives is to use a system of encrypted memory. The data stored in memory, would appear to be effectively random without access to the keys and decryption mechanism. If data is encrypted with a strong algorithm which induces variability in the encrypted data, it is a practical impossibility to brute force decode the data without access to the key. Improperly secured key information compromises the encrypted data stored, a level of tamper security is required to prevent operation outside a specified range of operation thwarting some probing or reverse engineering attacks. A concept design specification will be delivered at the conclusion of the project.