SBIR/STTR Research Award
Secure Memory for Anti-Tamper (AT) Application
Award amount
$99,999Program and phase
SBIR · Phase IAward year
2006Award details
- Awarding agency
- Department of Defense
- Branch
- Army
- Recipient company
- Lewis Innovative Technologies, Inc.
- Proposal award date
- 2006-06-05
- Contract end date
- 2007-06-05
- UEI
- CV3PNJV2VVX3
- Solicitation number
- 2005.3
- Topic code
- OSD05-A11
Research abstract
LIT proposes developing non-volatile memory constructed from blocks of SRAM configured for fast block erasure using a parallel erase technique. LIT proposes a memory controller capable of quickly rendering the data useless by means of a proprietary technique.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Physical Uncloneable Function (PUF) Encryption Key
- Reconfigurable Memory or Central Processing Unit (CPU) Instruction Architecture
- Anti-Tamper Technology for Missile Defense
- Anti-Reverse Engineering (RE) Techniques
- Field Programmable Gate Array (FPGA) Physical Unclonable Functions
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Zero-Remanence Anti-Tamper Cryptokey Storage Device
- Zero-Remanence Anti-Tamper Cryptokey Storage Device
- Anti-Tamper Optical Secure Read/Write/Erase Memory
- Secure Memory for Anti-Tamper (AT) Application
- Tamper Proof, Erase-on-Demand Memories
Research funding history
27 SBIR/STTR records share this UEI (2001–2015). Reported award amounts total $10,693,020. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense