AN/SLQ-32 IFM/CFR upgrade

We present a method for upgrading the AN/SLQ-32 IFM/CFR that is applicable to the subject of the solicitation. The method addresses the measurement of frequency and pulse-width in the presence of digitally modulated CW and HPRF interference. We also discuss the available technology with which to implement digital processors capable of hosting real-time implementations of practical algorithms based on these methods. The hardware design employs a full-mesh serial backplane for card-to-card data transfers and field programmable gate arrays for most of the real-time signal processing. The architecture of a digital processor takes the form of a parallel processing network specifically tailored to match the natural data flow structure of the algorithm it will host. We propose to design the firmware tailored for this application and define a Phase II demonstration of the upgraded IFM algorithms operating in real-time on a hardware platform.