A Hardware Implementation of Multi-Level Security in Real Time Shared-Memory Avionic Systems

Rydal Research proposes to develop a low cost, high performance, shared memory multi-level secure data network capable of supporting data rates in the range of 10 Gbps per link. The network is based on a high-performance COTS networking protocol with appropriate extensions and enhancements to support multi-level security. The goal of the Phase II effort is to develop a complete set of building blocks needed to implement an MLS system in the military or commercial environment. To achieve this goal a number of key components will be developed in Phase II. First, a high performance low-power MLS switch ASIC will be designed and fabricated, based on the FPGA version developed under Phase I. This switch will work directly with MLS-enabled processors for an efficient low-chip-count solution. In addition, Rydal will continue to work through the relevant trade association to address Navy requirements in future protocol extensions and application notes and to ensure that these developments are compatible with the requirements of certifying agencies. To support non MLS-enabled processors Rydal will design and fabricate a generic MLS- endpoint bridge chip. This will be based on the bridge chip FPGA demonstrated in Phase I but with a PCI Express core replacing the existing bus interface. The development of this component will maximize flexibility and applicability.