A Hardware Implementation of Multi-Level Security in Real Time Shared-Memory Avionic Systems

Rydal Research proposes to develop a high speed low-latency hardware-based implementation of multi-level security in a high-performance COTS protocol. The proposed method involves adding a sensitivity field to the Transport Layer header. Support for packet filtering will be added within the existing protocol specification. An additional error code will be developed to indicate errors and security violations in the filtering hardware. One or more real-time operating systems will be selected and the sensitivity level conveyed to the network interface via the operating system kernels. Fine-grain modeling and simulation will be used to determine the impact of the protocol modifications on system performance. An analysis will also be performed to determine the susceptibility and response of the protocol to intentional and unintentional security violations. All components needed to implement a complete system will be developed and demonstrated in Phase I in an FPGA-based prototype using Rydal's reconfigurable computing platform and low-latency network switch. Flexible, robust, and easy-to-use software support will also be provided for system bring-up, maintenance, and troubleshooting. RapidIO will be used for the initial implementation but the techniques developed will be sufficiently flexible that they can be used with any other high-performance protocol.