High Speed Readout for Photodiode Focal Plane Arrays

The objective of this proposal is to design a high-speed readout for photodiode focal plane arrays with sub-nanosecond sampling rates. For active sensing applications, current architectures using CMOS technology can sample up to 400 MHz (2.5 ns). However, photodetectors with bandwidth over 1 GHz, and sampling rates in excess of 1 GHz (less than 1 ns), are needed for numerous battlefield applications including 3-D laser radar, and coherent vibration measurements. In addition, large arrays (at least 16 x 16) are desirable for increased resolution. Current technology bonds a diode array to a CMOS control circuit, causing the speed of the detector to be limited by the CMOS circuitry and architecture. The purpose of this proposal is to significantly increase the speed of the sampling circuit by using InP-based electronics, and monolithically integrating the circuit with an InP-based phototdiode array. This integrated PIN/HBT approach could dramatically increase the sampling rate of the ROIC well above 5 GHz (0.2 ns).